This invention relates to a semiconductor device and, more particularly to a multilayered interconnection of a semiconductor device and a method for forming the same, which can reduce the contact resistance and improve the reliability of a semiconductor device and which is suitable for high density integration of semiconductor devices.
As the density of integration of a semiconductor device becomes higher with the minimum width of the semiconductor device submicronized to below 0.5 .mu.m, a contact hole for interconnecting an upperside connection layer and an underside connection layer has been also submicronized, with a ratio of the depth to the width of the contact hole increased.
Therefore, due to degradation of step coverage in the case where an interconnection layer is formed in the contact hole with a conventional physical deposition method of a sputtering method, there have been problems of increase of a contact resistance and reduction of an endurance by electromigration and stress migration.
As the methods of forming a plug in the contact hole for improving the step coverage of the contact hole, there are an art of forming the plug in the contact hole by depositing tungsten on an insulation film including the contact hole and subjecting the tungsten to etch back to a depth more than the deposited thickness, and an art of tungsten or aluminum selective growth in which a plug of tungsten or aluminum is selectively grown only in the contact hole.
FIGS. 1A to 1C show a conventional multilayered interconnection, wherein FIG. 1A shows a sectional view, FIG. 1B shows a plan view, and FIG. 1C shows a contact between an upperside interconnection layer and a plug.
Referring to FIG. 1A and FIG. 1B, an underside interconnection layer 13 is formed to be in contact with the upperside interconnection layer 18 through a plug 17 formed in a contact hole. An interlayer insulation film 14 is formed between the upperside, and underside interconnection layers 13 and 18 for insulating them, and an underside insulation film 12 is formed between a substrate 11 and the underside interconnection layer 13 also for insulating them. The reference number 15' represents a contact.
The multilayered interconnection has the plug 17 for electric interconnection of the upperside and underside interconnection layers 13 and 18. Because the upperside interconnection layer 18 is in contact with the upper part of the plug 17, a contact area between the upperside interconnection layer 18 and the plug 17 is related to the dimension of the contact hole. If the dimension of the contact hole is a square of a.times.a, the area of contact A.sub.0 is A.sub.0 =a.times.a.
FIGS. 2A to 2E show processes for forming the multilayered interconnection of the semiconductor device of FIG. 1. As shown in FIG. 2A, by forming an underside insulation film 12 on a semiconductor substrate 11, and forming and patterning a metal layer on the underside insulation film 12, an underside interconnection layer 13 is formed.
As shown in FIG. 2B, an interlayer insulation film 14 is formed on the underside insulation film 12 including the underside interconnection layer 13. A part of the interlayer insulation film 14 on the underside interconnection layer 13 is etched with a photoetching process to form a contact hole 15.
As shown in FIG. 2C, a conductive material 16 is deposited so as to fill the contact hole 15 with a blanket deposition A.sub.0 shown in FIG. 2D the conductive material 16 is, etched back into a plug 17.
In the plug formation process of FIGS. 2C and 2D, the plug can be formed by growing a conductive material in the contact hole with a selective growth method instead of the above method.
As shown in FIG. 2E, by forming and patterning a metal layer on the plug 17 and the interlayer insulation film 14, an upper interconnection layer 18 is formed. Thus, the upperside interconnection layer 18 and the underside interconnection layer 13 are electrically connected through the plug 17.
However, the foregoing multilayered interconnection has following problems.
First, since the conventional multilayered interconnection is in contact with the upperside interconnection layer only at the upper part of the plug, the contact area between the upperside interconnection layer and the plug is reduced as the dimension of the contact hole is reduced. Accordingly, the conventional multilayered interconnection has had a problem of increased contact resistance due to the reduced contact area.
Second, in cases when misalignments of a contact mask for forming the contact hole and/or of a mask for forming the upperside interconnection layer should happen, the upperside interconnection layer can not be in full contact with the upper part of the plug, and with the contact area reduced the more, there has been a problem of the more increase of the contact resistance. Moreover, since the incomplete contact between the upperside interconnection layer and the plug causes not only an incomplete electrical connection between the upperside interconnection layer and the underside interconnection layer, but also, sometimes, results in an opening between the upperside interconnection layer and the plug. This leads to a defective device and a problem of significant degradation of the device reliability.
Third, in the case where the plug is formed in the submicron contact hole with a blanket deposition process and an etch back process, at depositing a conductive material with the blanket deposition process, since a full filling of the conductive material into the contact hole is hardly obtainable, as shown in FIG. 3A, a seam opening, as shown in FIG. 3B, can be formed after the etch back process.